In a nutshell: The 6th-generation AMD Epyc processors, codenamed Venice, will be the first high-performance computing product built using TSMC's 2nm (N2) process node. Team Red also confirmed that TSMC's new Fab 21 facility in Arizona has successfully validated 5th-generation Epyc silicon and will handle some of the chip production in the United States. Venice, built on AMD's upcoming Zen 6 microarchitecture, represents a major milestone in the company's data center roadmap and remains on track for release next year. While AMD withheld further details, it confirmed the silicon has been taped out and brought up – indicating the CCD powered on successfully and passed initial tests. Leaked details indicate that Epyc Venice CPUs will use the new SP7 socket, replacing the SP6 (LGA 4094) platform in Zen 4c-based Siena processors. Rumors also point to support for both 12-channel and 16-channel memory configurations, along with faster DIMM speeds on the PCIe Gen 6 interface. The new N2 process node marks TSMC's first use of gate-all-around (GAA) nanosheet transistors. The company calls it the industry's most advanced technology for density and energy efficiency, claiming the nanosheet structure delivers a 15 percent performance boost at the same voltage or a 24 to 35 percent drop in power use compared to the older 3nm finFET (N3) process. The announcement comes on the heels of Intel's delay of its Xeon "Clearwater Forest" data center processors, now expected in the first half of 2026. Initially slated for release this year and based on the company's 18A process technology, the chips will arrive at least a few quarters late – even if Intel sticks to its revised timeline. Unlike Clearwater Forest, Intel's Panther Lake CPUs for client PCs, built on the 18A process, remain on track for release later this year. Like other recent Intel chips, Panther Lake will use a hybrid architecture combining Cougar Cove performance and Skymont efficiency cores. The processors will also feature the Xe3 'Celestial' GPU, offering up to 12 Xe3 cores. // Related Stories